1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to a high-speed algorithmic pattern generator for an integrated circuit tester.
1. Description of Related Art
A typical integrated circuit (IC) tester includes a separate channel connected to each pin of an IC under test. The tester organizes an IC test into a succession of test cycles. During each test cycle each channel may transmit a test signal to an IC pin or may sample an IC output signal produced at the pin to determine whether it is of an expected state. Before the start of each test cycle each channel receives a data value (a "vector") telling it when and how to change the state of its input test signal during the cycle or when to sample the IC output signal during the cycle and indicating the expected IC output signal state.
Each channel of a "per pin" IC tester includes its own pattern generator for providing a vector at the start of each test cycle. A simple pattern generator includes a random access memory (RAM) storing vectors needed for successive test cycles at successive addresses and a counter for incrementing the vector memory address before the start of each test cycle so that the vector memory reads out the vectors in succession. As ICs have become more complex, the number of test cycles (and vectors) needed to test an IC continues to increase. In many cases it has become impractical to provide a vector memory large enough to store a vector for each test cycle. However since many tests involve repetitive operations, channels often require repetitive sequences of vectors. More sophisticated pattern generators replace the counter with an instruction processor and an instruction memory storing an algorithmic program. The program tells the instruction processor how to address the vector memory during a test. Loop and subroutine call instructions tell the instruction processor to repeatedly access various vector sequences stored in the memory when repetitive test activities are to be carried out.
As the IC's operating frequencies continue to increase, the test cycle length must decrease in order to provide high frequency input signals to the IC and in order to sample IC output signals at high frequencies. When a vector memory must read out a vector at the start of each test cycle, the vector memory must also operate at higher frequencies. However large, high frequency RAMs are expensive and in some cases available RAMs simply aren't as fast as some of the ICs being tested. One solution to this problem has been to store more than one vector at each vector memory address so that the vector memory does not have to read out a vector at the start of every test cycle. For example if 128 vectors are stored at each vector memory address, then it is necessary to access the vector memory only once every 128 test cycles. In such case the vectors read out of the vector memory are written into a relatively small high-speed cache memory and then read back out of cache memory one vector at a time as they are needed.
While cache memories resolve the slow vector memory problem, they restrict the ability of algorithmic pattern generators to perform loops and calls. Since a vector must be written into cache memory sometime before it is needed, the caching system would have to somehow anticipate when a subroutine call or return or a loop return to start is going to occur. Since a vector must be supplied for every test cycle, and since it takes longer than one test cycle to access the vector memory, a call or return instruction that causes a jump in vector sequencing cannot direct the cache memory to obtain the first vector of a loop or call sequence directly from the vector memory. Some pattern generators can perform loops or calls by jumping to the start of a vector sequence already stored in cache memory, but the number of vectors included in the loop or subroutine is limited by the size of the cache memory.
When even cache memory is not fast enough to supply vectors at the test cycle frequency, "doublet mode" of tester operation has been employed. In the doublet mode, a test cycle is divided into two segments and the vector produced by the pattern generator at the start of a test cycle indicates channel operations that are to be carried out in each of the two segments. Thus the test frequency, the frequency at which test activities are carried out at the IC pins, is twice the vector output frequency of the cache memory. However doublet mode operation greatly complicates programming of algorithmic pattern generators because, since vectors are generated only on test cycle boundaries, loops and subroutines must start and end only on boundaries between test cycles and not on the boundary between the two segments of a test cycle. Thus when we program a doublet mode tester we have to keep track of the segment in which each test activity occurs and avoid attempting to start or end a loop or subroutine call or return with an activity occurring during the second segment of a test cycle. This makes tester programming very difficult, particularly when repetitive test sequences involve an odd number of test activities.
What is needed is an integrated circuit tester employing an algorithmic vector pattern generator using cache memory, which operates at a test frequency that is a multiple of the output frequency of the cache memory, but which places no restrictions on timing or length of loops and calls.